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Hawk12 Posts: > 500

Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.

This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:

We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.

In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.

The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").

Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.

Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.

Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.

The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.

It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other.
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Posted: 2023-06-18 01:22:43
Edit : Quote

xpr Posts: 328


On 2023-06-18 01:22:43, Hawk12 wrote:
Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.

This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:

We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.

In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.

The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").

Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.

Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.

Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.

The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.

It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other.

Could you share the original article?
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Posted: 2023-06-18 10:28:31
Edit : Quote

Hawk12 Posts: > 500


On 2023-06-18 10:28:31, xpr wrote:

On 2023-06-18 01:22:43, Hawk12 wrote:
Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.

This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:

We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.

In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.

The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").

Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.

Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.

Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.

The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.

It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other.

Could you share the original article?



got this from weibo ... I just crtled c + crtled v it
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Posted: 2023-06-18 12:08:59
Edit : Quote

lewisken02 Posts: 23


On 2023-06-18 10:28:31, xpr wrote:

On 2023-06-18 01:22:43, Hawk12 wrote:
Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.

This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:

We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.

In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.

The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").

Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.

Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.

Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.

The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.

It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other.

Could you share the original article?




Heres the source
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Posted: 2023-06-18 19:35:34
Edit : Quote

Hawk12 Posts: > 500

There is video on youtube (Channel is Kai W).

He claim over 4h of 4K@60 and phone only stopped recording because of battery was low.


😱😱😱😱😱😱😱😱
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Posted: 2023-06-28 21:31:08
Edit : Quote

tai020381 Posts: > 500

Vs xperia pro i.

https://youtu.be/ZzLIlGVL3UI
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Posted: 2023-07-07 18:04:44
Edit : Quote

cool_sauce Posts: 345


On 2023-07-07 18:04:44, tai020381 wrote:
Vs xperia pro i.

https://youtu.be/ZzLIlGVL3UI


Seems about right. New sensor gives bout the same quality as Type 1 sensor from RX/PRO-I. There is still tons of more postprocessing on 1V compared to PRO-I but we not gonna pixel peep. Unless extra shortcut button and lanyard loop or the design of the device is something you really desire there is no need to get PRO-I anymore. Or if you shoot in Cinema Pro then variable aperture is like godsend but no one records video in Cinema Pro honestly (too much setup time for an avg output results). Seems like my PRO-I will be going bye bye once the fall comes.
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Posted: 2023-07-10 12:25:46
Edit : Quote

Hawk12 Posts: > 500


On 2023-07-10 12:25:46, cool_sauce wrote:

On 2023-07-07 18:04:44, tai020381 wrote:
Vs xperia pro i.

https://youtu.be/ZzLIlGVL3UI


Seems about right. New sensor gives bout the same quality as Type 1 sensor from RX/PRO-I. There is still tons of more postprocessing on 1V compared to PRO-I but we not gonna pixel peep. Unless extra shortcut button and lanyard loop or the design of the device is something you really desire there is no need to get PRO-I anymore. Or if you shoot in Cinema Pro then variable aperture is like godsend but no one records video in Cinema Pro honestly (too much setup time for an avg output results). Seems like my PRO-I will be going bye bye once the fall comes.



For someone that does not care about having the latest, now at least in USA the pro-i is something $400 cheaper.



Bonus: 1v was top seller on e-shop of au (japanese carrier) in june, ahead of iphones and pixels.
[ This Message was edited by: Hawk12 on 2023-07-11 12:59 ]

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Posted: 2023-07-10 13:21:57
Edit : Quote

MyP910 Posts: > 500

I got my Xperia 1V. It is really good. Significantly better than 1iv.
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Posted: 2023-07-13 16:01:07
Edit : Quote

goldenface Posts: > 500


On 2023-07-13 16:01:07, MyP910 wrote:
I got my Xperia 1V. It is really good. Significantly better than 1iv.



Congratulations. What do you like best about the V?
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Posted: 2023-07-14 01:04:17
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